[libre-riscv-dev] [Bug 178] first coriolis2 tutorial, workflow and "test project" page

[bugzilla-daemon at libre-riscv.org]

http://bugs.libre-riscv.org/show_bug.cgi?id=178

--- Comment #19 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
i added mk/synthesis-yosys.mk from the 6502/cmos bench, substituting
"verilog" with "ilang".  shoooould be good to go?

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