[libre-riscv-dev] [Bug 178] first coriolis2 tutorial, workflow and "test project" page

bugzilla-daemon at libre-riscv.org bugzilla-daemon at libre-riscv.org
Fri Feb 14 17:26:39 GMT 2020


--- Comment #17 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
(In reply to Tobias Platen from comment #16)
> I was using an old version of the cell libraries. 
> I solved the problem using the new ones from alliance-check-toolkit.
> Now python3 part_sig_add.py will produce valid output.

ahh briiilliant, that's really good news!  can you quickly make sure that
the wiki page has what is needed?

oh, can you add the Makefile as well to the repo?  i see coriolis2/katana.py,
settings.py and __init__.py, no Makefile yet?

also... oh, although i personally like the way you did it as a python program,
(run_yosys() in examples/part_sig_add.py) let's keep that in the Makefile
format #include-style, because we'll be using it quite a lot?

unix rule, "one command does one thing and does it well".

if you don't beat me to it (i have a phone call to make, to alain),
i will experiment, here, in a bit, with setting the module name to
something other than "top" in create_ilang, it _should_ work when
setting an alternative, at which point we can take that copy of
mk/synthesis-yosys.mk and really pretty much cut/paste it exactly,
simply replacing "read_verilog" with "read_ilang".

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