[libre-riscv-dev] Routing a first nmigen disign with Corilis

[Jean-Paul Chaput]

Depends on the zoom level and of the fact that you ask to see
the inside of the cells.

To actually see the transistors:
   Tools -> Controller -> Filter Tab -> check "Process Terminal Cells"

You can also tweak the layer display:
   Tools -> Controller -> Layers & Go


On Tue, 2020-02-11 at 16:18 +0000, Luke Kenneth Casson Leighton wrote:
> okaaay so make lvx succeeds (hooray!), make cgt shows the "thing" -
> interestingly i'm not seeing any actual cells (no transistors are
> visible), just the routing, is that right?
> 
> l.
> 
> _______________________________________________
> libre-riscv-dev mailing list
> libre-riscv-dev at lists.libre-riscv.org
> http://lists.libre-riscv.org/mailman/listinfo/libre-riscv-dev
-- 

      .-.     J e a n - P a u l   C h a p u t  /  Administrateur Systeme
      /v\     Jean-Paul.Chaput at lip6.fr
    /(___)\   work: (33) 01.44.27.53.99              
     ^^ ^^    cell:      06.66.25.35.55   home: 09.65.29.83.38

    U P M C   Universite Pierre & Marie Curie
    L I P 6   Laboratoire d'Informatique de Paris VI
    S o C     System On Chip