[libre-riscv-dev] Routing a first nmigen disign with Corilis

Jean-Paul Chaput Jean-Paul.Chaput at lip6.fr
Tue Feb 11 17:37:53 GMT 2020

Depends on the zoom level and of the fact that you ask to see
the inside of the cells.

To actually see the transistors:
   Tools -> Controller -> Filter Tab -> check "Process Terminal Cells"

You can also tweak the layer display:
   Tools -> Controller -> Layers & Go

On Tue, 2020-02-11 at 16:18 +0000, Luke Kenneth Casson Leighton wrote:
> okaaay so make lvx succeeds (hooray!), make cgt shows the "thing" -
> interestingly i'm not seeing any actual cells (no transistors are
> visible), just the routing, is that right?
> l.
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      /v\     Jean-Paul.Chaput at lip6.fr
    /(___)\   work: (33)              
     ^^ ^^    cell:   home:

    U P M C   Universite Pierre & Marie Curie
    L I P 6   Laboratoire d'Informatique de Paris VI
    S o C     System On Chip

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