[libre-riscv-dev] [Bug 165] New: Formally verify the FPCMP (FEQ, FLE, FLT) module

[Luke Kenneth Casson Leighton]

On Monday, February 3, 2020, Michael Nolan <mtnolan2640 at gmail.com> wrote:

> Luke Kenneth Casson Leighton <lkcl at lkcl.net> writes:
>
> >
> > wanna give it a shot?
>
> So it does work, sort of. If I set the crossbar RHS to 1 and set the gt
> inputs to 0, it gives the correct output for the active outputs, however
> the outputs that should get set to a constant 0 get set to a constant 1
> instead


that's why i suggested trying the Full Adder from PartitionPoints.

l.



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