[libre-riscv-dev] [Bug 165] New: Formally verify the FPCMP (FEQ, FLE, FLT) module

Michael Nolan mtnolan2640 at gmail.com
Mon Feb 3 18:33:11 GMT 2020

Luke Kenneth Casson Leighton <lkcl at lkcl.net> writes:
>> My idea for partitioned gt looks pretty similar, with an AND gate
>> and OR
>> gate cascaded instead of the single OR (or AND for the noninverted
>> circuit) in the partitioned eq circuit.
>> https://i.imgur.com/azx2hpQ.jpg
> oo i like it.

It would almost work for eq as well. I think if the gt inputs are set to
0 and the right input to the crossbars is set to 1 it would be
equivalent to the equals case. However, that would mean using actual


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