[libre-riscv-dev] [Bug 165] New: Formally verify the FPCMP (FEQ, FLE, FLT) module

[bugzilla-daemon at libre-riscv.org]

http://bugs.libre-riscv.org/show_bug.cgi?id=165

            Bug ID: 165
           Summary: Formally verify the FPCMP (FEQ, FLE, FLT) module
           Product: Libre Shakti M-Class
           Version: unspecified
          Hardware: PC
                OS: Windows
            Status: CONFIRMED
          Severity: enhancement
          Priority: ---
         Component: Formal Verification
          Assignee: lkcl at lkcl.net
          Reporter: mtnolan2640 at gmail.com
                CC: libre-riscv-dev at lists.libre-riscv.org
   NLnet milestone: ---

A formal proof for the fpcmp module can be found here:
https://git.libre-riscv.org/?p=ieee754fpu.git;a=blob;f=src/ieee754/fpcmp/formal/proof_fpcmp_mod.py;h=4f3d273ebbff4ea2c5133134383600d14e8c2683;hb=HEAD

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