[libre-riscv-dev] daily kan-ban update 04aug2020

[Luke Kenneth Casson Leighton]

On Wed, Aug 5, 2020 at 7:55 PM Tobias Platen
<libre-soc at platen-software.de> wrote:
>
> On Wed, 5 Aug 2020 19:39:20 +0100
> Luke Kenneth Casson Leighton <lkcl at lkcl.net> wrote:
>
> > this means that instead of having a 16 bit mask to cover 128 bits of
> > data,  a whopping *128* bit mask is needed and that's precisely what
> > we do not want.
> I think now understand my mistake in thinking and how to solve the problem.

cool.

basically, the mask is wishbone "sel", set to a granularity of 8 bits
(one byte) per bit of "sel".

if you read the wishbone spec, concentrating on when "sel" is not just
a single bit, you'll see clearly what is needed.

we are propagating that byte-per-bit mask RIGHT THE WAY THROUGH THE
ENTIRE DESIGN.

it starts at LD/ST - right back when a byte, half-word, word or dword
LD/ST is requested - and goes - will go - through the ENTIRE design

through PortInterface.

through LDSTSplitter.

through DataMerger.

through the L1 cache which will need to respect byte-level masks

through the L2 cache which will need to respect byte-level masks.

through the wishbone buses which will need to respect byte-level masks

through to the DDR / SDR bus which will *ALSO* need to respect byte-level masks.

eeeeverything and i *mean* everyting.

SDR (DDR1, SDRAM) does in fact accept byte-level masks.

if at any time we encounter a memory system which does *NOT* respect
byte-level masks, then we have a problem and will have to rethink.

l.