[libre-riscv-dev] daily kan-ban update 04aug2020

Tobias Platen libre-soc at platen-software.de
Wed Aug 5 17:48:11 BST 2020


On Wed, 5 Aug 2020 18:40:58 +0200
Tobias Platen <libre-soc at platen-software.de> wrote:

> On Tue, 4 Aug 2020 18:32:34 +0100
> Luke Kenneth Casson Leighton <lkcl at lkcl.net> wrote:
> 
> > On Tue, Aug 4, 2020 at 6:19 PM Tobias Platen
> > <libre-soc at platen-software.de> wrote:
> > >
> > > today:
> > >
> > > unit test for DualPortSplitter
> > 
> > ok great.  btw you saw that i had to revert a commit that you made:
> Yes, I saw 
> > please do ensure that you commit code that is "working" or at least
> > doesn't cause other people to not be able to do "work".  i've had to
> > do this three times now.
> > 
> > as best i can tell when i wrote the unit test for LDSTSplitter, the
> > "logic" behind LDSTSplitter is correct, however the mask works on
> > *bits* not bytes (sigh).
That might be the reason why I get an error when running the unit tests:
LenExpand 4 1 unsigned(16)
LenExpand 4 1 unsigned(16)
ldm 255 0b11010011
dlm 15 0b1100
dmask 0b11111111000000000000
dmask1 0b1111
dmask 0b1111000000000000
lds
send_ld
waiting
ld data1 0b11010011 0b11000000000000 12 0b1111000000000000
ld data2 16 0b0 0b1101
0b11 0b11010011
Traceback (most recent call last):
  File "addr_split.py", line 270, in <module>
    sim(dut)
  File "addr_split.py", line 261, in sim
    sim.run()
  File "/home/isengaara/Hacking/lSOC/TEST/nmigen/nmigen/sim/pysim.py", line 382, in run
    while self.advance():
  File "/home/isengaara/Hacking/lSOC/TEST/nmigen/nmigen/sim/pysim.py", line 371, in advance
    self._real_step()
  File "/home/isengaara/Hacking/lSOC/TEST/nmigen/nmigen/sim/pysim.py", line 347, in _real_step
    process.run()
  File "/home/isengaara/Hacking/lSOC/TEST/nmigen/nmigen/sim/_pycoro.py", line 120, in run
    self.coroutine.throw(exn)
  File "/home/isengaara/Hacking/lSOC/TEST/nmigen/nmigen/sim/_pycoro.py", line 61, in run
    command = self.coroutine.send(response)
  File "/home/isengaara/Hacking/lSOC/TEST/nmigen/nmigen/sim/pysim.py", line 265, in wrapper
    yield from process()
  File "addr_split.py", line 232, in send_ld
    assert ld_data_o == data
AssertionError
make: *** [Makefile:4: test_ldst_splitter] Fehler 1
I'll investigate that.
> > 
> > also: the left port needs to be for when addr[4] == 0 and the right
> > port for when addr[4] == 1.  this is achieved with a crossbar on
> > *both* the LD *and* ST data.
> > l.
> > 
> > _______________________________________________
> > libre-riscv-dev mailing list
> > libre-riscv-dev at lists.libre-riscv.org
> > http://lists.libre-riscv.org/mailman/listinfo/libre-riscv-dev
> 
> 
> -- 
> Tobias Platen <libre-soc[at]platen-software[dot]de>
> 
> _______________________________________________
> libre-riscv-dev mailing list
> libre-riscv-dev at lists.libre-riscv.org
> http://lists.libre-riscv.org/mailman/listinfo/libre-riscv-dev


-- 
Tobias Platen <libre-soc[at]platen-software[dot]de>



More information about the libre-riscv-dev mailing list