[libre-riscv-dev] daily kan-ban update 03aug2020

Luke Kenneth Casson Leighton lkcl at lkcl.net
Mon Aug 3 18:46:46 BST 2020




* nmigen IRC meeting (in 15 mins)
* linked DMI interface to core and got reset, start and stop working.

i need to test single-step as well as add regfile reading and being able to
get MSR and the PC.

at that point i can modify the litex sim.py to put either core in
singlestep mode and dump out registers and the PC, sequentially.


crowd-funded eco-conscious hardware: https://www.crowdsupply.com/eoma68

More information about the libre-riscv-dev mailing list