[libre-riscv-dev] daily kan-ban update 01aug2020

Luke Kenneth Casson Leighton lkcl at lkcl.net
Sat Aug 1 18:58:55 BST 2020




* exploring litex libresoc simulation, found several bugs


* looked at shiftrot formal proof
* continued litex simulation investigation

finding out what is going on in litex is hampered significantly by not
being able to do side-by-side comparisons.

therefore what i am going to do is add a dmi interface to libresoc and get
the litex sim to single-step then dump registers.  with a compatible dmi
interface the same sim code FSM will be useable on both types of core.

discrepancies should then be easy to spot by using diff on the two debug

at that point i will know which instruction is wrong, where right now it is
excruciating guesswork.


crowd-funded eco-conscious hardware: https://www.crowdsupply.com/eoma68

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