[libre-riscv-dev] HTTaP and Design for Test (was Re: circuitjs)

whygee at f-cpu.org whygee at f-cpu.org
Tue Apr 28 20:37:07 BST 2020

On 2020-04-28 17:35, Luke Kenneth Casson Leighton wrote:
> the actual
> server-side implementation of a JSONRPC server was done in a mere *50*
> lines of code.  25 of those lines involved exception/error handling!
> other JSONRPC servers that i've seen are thousands of lines of
> completely unnecessary code.

speaking of which : did I mention I rebooted the design of my HTTaP 
server ?

http://httap.org : It's a protocol for TAP over (hidden in) HTTP.

It's currently live on http://httap.org:60075 if you want to see
(the port number may change and it's not running 24/7)

The total number of lines in C is 1203 for now and I have not yet
added much support for user-provided functions but don't laugh yet.
it's convoluted but really required !

It was initially designed about 8 years ago to run INSIDE GHDL and
control/report VHDL simulations. For example you provide your own user
"words" to control the state of input and output signals then "plug" the
commands to actual VHDL code. Then write the testbenches in JS
or whatever, co-simulate with FPGA or compare between different

My recent designs include a TAP (Test Access Port) that exactly
mimics the real pins that would be provided on the outside of the
FPGA or ASIC, it could be JTAG or anything convenient. I use a
half-duplex SPI-like interface to send and receive control/status
data, inject and exfiltrate given signals from a design...

The HTTaP interface is very friendly to microcontrollers and Raspberry 
which is an obvious choice for this kind of application.

The protocol/interface looks the same to the JS GUI, just change the 
Thus, the emulation, the simulation, the FPGA and the ASIC look
exactly the same. That's "design for test".

It's even a great idea to start the design (and assembly of all the 
from the TAP interface itself, building from there and expanding.
This makes sure ALL circuits can be thoroughly tested and accessed,
little by little while the circuit is built, not at the last moment,
which is a great insurance of having your chips tested and running
very fast after delivery from the fab.

I hope this sparks some more ideas and boosts Libre-SOC :-)

> l.

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