[libre-riscv-dev] [Bug 288] intro post for powerpc-notebook.org and https://www.powerprogress.org/en/

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=288

Jacob Lifshay <programmerjake at gmail.com> changed:

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--- Comment #5 from Jacob Lifshay <programmerjake at gmail.com> ---
(In reply to Luke Kenneth Casson Leighton from comment #4)
> > The first iteration of LibreSOC targets a single-core at 180nm. Subsequent
> > generations target more cores at a smaller node size.
> 
> looks good.  i'd put "target multiple SMP cores" though.  "more cores"
> could mean "NUMA" or "SIMT".  SIMT is almost impossible to program for
> general-purpose, and NUMA is a royal pain, memory-wise.

Sounds good, though, it would be NUMA if we have multiple chips wired together
using OmniXpress or similar.


Also, we should be consistent spelling Libre-SOC with the hyphen like we
agreed.

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