[libre-riscv-dev] [Bug 257] Implement demo Load/Store queueing algorithm

bugzilla-daemon at libre-soc.org bugzilla-daemon at libre-soc.org
Wed Apr 22 14:06:43 BST 2020


--- Comment #26 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
L1 cache concept, go for it - that's really straightforward and standard,
although important to appreciate that 16 *byte* level read/write-enable lines
will come through from the Function Units.

if you can also do a non-standard-wishbone-128 to standard-wishbone-64
bit "funnel", that analyses the 16 byte-level read/write-enable lines,
splitting them into two halves covering the LO-64-bit and HI-64-bit
that would fit well.

actually to be honest at the 128-bit-level it doesn't even need to be
Wishbone, which may make design easier.

another "easier" way may be to simply have *FOUR* 64-bit Wishbone

* L1 left LO-64
* L1 left HI-64
* L1 right LO-64
* L1 right HI-64

then we "jam" those down onto a single 64-bit Wishbone interface
using a standard Wishbone Bus arbiter

L0 cache/buffer, give it a little time for some review / thought
as i just found a mistake in the L0 cache/buffer design and had
to adjust it:

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