[libre-riscv-dev] [Bug 288] intro post for powerpc-notebook.org and https://www.powerprogress.org/en/

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=288

--- Comment #2 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
(In reply to Yehowshua from comment #1)
> Something Like This:
> 
> LibreSOC is an Open Hardware and Open Software project that aims to deliver
> a physical quad core 180nm POWER compliant SOC that comes complete with a

no, single-core.  we're not doing quad-core, it will require something
like 160 mm^2 and that would cost around USD $60,000 just on its own.
not to mention, the power consumption would be immense, well beyond
what a standard low-cost JEDEC QFP package could handle.

we're keeping it to single-core, no SMP, no L2 cache.
https://libre-soc.org/3d_gpu/180nm_single_core_testasic_memlayout.jpg

the *next* version is quad-core, 28-45nm, full SMP.

-- 
You are receiving this mail because:
You are on the CC list for the bug.