[libre-riscv-dev] morphing 6600 code to use power decoder

[Luke Kenneth Casson Leighton]

https://libre-soc.org/3d_gpu/multi_bus_arbiter.png

i'm trying to design a multi-bus arbiter which routes:

* multiple banks of src1, src2, src3
* to ANY register-file read-port 1, read-port 2, read-port 3.

at the moment we have:

* multiple banks of src1, src2, src3
* read-port 1 has an INDEPENDENT PriorityPicker to manage access from src1
* read-port 2 has an INDEPENDENT PriorityPicker to manage access from src2
* read-port 3 has an INDEPENDENT PriorityPicker to manage access from src3

the actual arbitration can be done as "select" lines, and, once done,
they can be easily used to enable ORing of data onto buses.

am i overthinking this?

is it as simple as just flattening the multiple banks of src1, src2,
src3 into a linear 1D line of requests?  so if there are 6 banks each
with src1,src2,src3 simply flatten that to 18 requests (for access to
the 3 read-ports)?

l.