[libre-riscv-dev] libre-soc status: simulator and hardware "first instruction" execution

Luke Kenneth Casson Leighton lkcl at lkcl.net
Sat Apr 11 12:33:23 BST 2020

hurrah, after a *lot* of preparation creating various components, the
python-based simulator (only 10 days old) "executed" its first
instructions last week, and, on the basis of that work, the hardware
version was adapted to use the same code as used and tested by the
simulator, and also executed its first actual POWER-decoded
instruction, today.

it was actually three instructions in the hardware: two addi and one
add.  the simulator has had add, addpcis, ld, st and mtcrf for around
a week.

the hardware engine - based on the Cray CDC 6600 superscalar
out-of-order architecture (yes, really) - has been operational for
almost a year, with an "internal" (test-only) micro-code that allowed
its operation, including speculative (single-path-cancellable rather
than dual-path cancellable) branches, LD/ST and basic arithmetic, to
be confirmed as functional and not corrupting data.

getting it to understand POWER ISA required replacing that test-only
micro-code, developed last year, with Anton's microwatt-based internal
decoder format.  thanks to Michael Nolan's help over the past couple
of months, that decoder was completed, tested, proven (via the
simulator) and was straightforward to drop in place.

we now need to plumb in additional instructions, and convert the LD/ST
and Branch ALUs to understand the microwatt Internal decode format.


crowd-funded eco-conscious hardware: https://www.crowdsupply.com/eoma68

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