[libre-riscv-dev] [Bug 267] The efficiency of adder/subtractor

bugzilla-daemon at libre-riscv.org bugzilla-daemon at libre-riscv.org
Tue Apr 7 14:15:46 BST 2020


--- Comment #6 from Jock Tanner <tanner.of.kha at gmail.com> ---
The idea is so simple yet so out-of-the-box! I feel like I'm in a Western
movie, while my partner is devising a get-rich-fast scheme:

− And where's the catch?
− There is no catch.

BTW is it patented?

(In reply to Luke Kenneth Casson Leighton from comment #5)
> https://git.libre-riscv.org/?p=ieee754fpu.git;a=blob;f=src/ieee754/
> part_mul_add/adder.py;h=e1849b4d25fc5ec4fc4473cc02b32f49dd5912b2;
> hb=77f150cff440bed025e2487b6f0fcda9f529290b#l108
> see the comment description there of how it works
> the "partitions" are done via the insertion of those "extra bits".
> those "extra bits" will be set to 0 to create a partition, and "1"
> to get a roll-over.
> so we're not *actually* "partitioning" into completely separate 8-bit adders.
> therefore i would hazard a guess that the (underlying 72-bit) adders are
> properly optimised by yosys "synth" command to give a decent fast adder,
> thus giving us the "best of both worlds".

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