[libre-riscv-dev] auto-generated simulator working??

Luke Kenneth Casson Leighton lkcl at lkcl.net
Sun Apr 5 21:19:59 BST 2020


moo?  it's working? holy cow!

    def test_load_store(self):
        lst = ["addi 1, 0, 0x0010",
               "addi 2, 0, 0x1234",
               "stw 2, 0(1)",
               "lwz 3, 0(1)"]

(SelectableInt(value=0x1234, bits=64),)
writing reg 3
reg  0 00000000 00000010 00001234 00001234 00000000 00000000 00000000 00000000
reg  8 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
reg 16 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
reg 24 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
SelectableInt(value=0x10, bits=64)
.
----------------------------------------------------------------------
Ran 3 tests in 1.918s

OK



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