[libre-riscv-dev] [Bug 269] auto-conversion / parser of POWER ISA Spec v3.0B

bugzilla-daemon at libre-riscv.org bugzilla-daemon at libre-riscv.org
Sun Apr 5 19:23:19 BST 2020


--- Comment #27 from Michael Nolan <mtnolan2640 at gmail.com> ---
Hmm. I figured I'd be able to create a class with multiple types of instruction
(so I can use loads and arithmetic instructions) like so:

class ISA(fixedarith, fixedload, fixedstore, ...):

But it seems that the different superclasses interfere with each other when
they initialize their instrs dict by doing "instrs = {}"

I tried removing that from each generated class, and adding it to the ISACaller
class, but now the generated classes can't find the dict from the superclass.
It looks like I can get it to sort of work by rearranging the generated class
like so: 

class fixedarith(ISACaller):
    def op_add(self, RA, RB):
        RT = RA + RB
        return (RT,)
    def __init__(self, dec, regs):
        super().__init__(dec, regs)

        self.instrs['add'] = (self.op_add, OrderedSet(['RA', 'RB']),
                OrderedSet(), OrderedSet(['RT']))

Is there a better way to do this?

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