[libre-riscv-dev] [Bug 269] auto-conversion / parser of POWER ISA Spec v3.0B

[bugzilla-daemon at libre-riscv.org]

http://bugs.libre-riscv.org/show_bug.cgi?id=269

--- Comment #25 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
oh, and one other thing... :)

the names of registers that are "recognised" are waay back in
decoder/pseudo/parser.py currently hard-coded

these need to be "lifted" from the current Form (Form-X)

however they will also need to be augmented by (p30):

* LR
* CTR
* CR (which can also be specified as CR0-CR7)
* XER
* FPSC

and TAR (p32)

oh, and instruction addresses:

* NIA (next)
* CIA (current)

and possibly some of the SPRs.

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