[libre-riscv-dev] [Bug 269] auto-conversion / parser of POWER ISA Spec v3.0B

bugzilla-daemon at libre-riscv.org bugzilla-daemon at libre-riscv.org
Sat Apr 4 21:37:05 BST 2020


--- Comment #21 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
(In reply to Michael Nolan from comment #20)
> (In reply to Luke Kenneth Casson Leighton from comment #16)
> > * as you saw in the bug #272 there's a problem with EXTS, which alerted
> >   me to adding the syntax (RA|0)
> If we're sure that power_decoder2 is correct, then all of the EXTS(...) and
> EXTZ(...) cases can be replaced with pdecode2.e.imm_data, because the
> decoder already handles sign/zero extending immediates.

mmm... yyeeees... except... that means modifying the pseudo-code which
comes directly from the spec.

this has two implications:

1) it's not a (strict) verification of the spec
2) as you point out, we'd be using something that we're not sure is correct

the more "direct", the better.

i'm not happy at the deviations from the spec that have had to be made!
the rather terrible solution is to have EXTZ and EXTS set the SelectableInt
bitlength to (say) 1,000,000 then use that to detect that when you get this:

   x + EXTS(d)

it means that in the addition, the rhs takes the bit-length of x.

okok we can't do 1,000,000 bits because in EXTS that would be a 1,000,000 bit
signed integer.  maybe... 256 bits or something.

i will modify SelectableInt so it is:

    def __add__(self, rhs):
          if rhs.bits == 256:
               rhs = SelectableInt(rhs.value, self.bits)

that will "do" as a workaround.

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