[libre-riscv-dev] [Bug 269] auto-conversion / parser of POWER ISA Spec v3.0B

[bugzilla-daemon at libre-riscv.org]

http://bugs.libre-riscv.org/show_bug.cgi?id=269

--- Comment #15 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
(In reply to Michael Nolan from comment #14)
> (In reply to Luke Kenneth Casson Leighton from comment #13)
> 
> > can i leave that with you?
> 
> yeah

star.  technically once that base class is in place  it should be possible to
go straight to dropping into internal_op.py

if you want to test out the new base class feel free to take one function from
one autogenerated file, as a test/dev case and hack something together that
works with interncal_op.

you will find however that much of decode2 is ignored (not useful).  the opcode
*name* (not InternalOp), and you will need the Form name.

cry_in flags, add1, neg, etc. all ignored because the pseudocode on a case by
case already does that. however carry_out on the other hand we need something
for that.


i am still doing stuff (have to add % operator) i will keep ploughing through
to get all of them compiled.

please do us a favour and apart from test cases don't add the compiled .py
files to the repo :) yes they are .py however they are not the source code: the
pseudocode is!

-- 
You are receiving this mail because:
You are on the CC list for the bug.