[libre-riscv-dev] [Bug 276] SR NAND Latch needed in nmigen

[bugzilla-daemon at libre-riscv.org]

http://bugs.libre-riscv.org/show_bug.cgi?id=276

--- Comment #3 from whitequark at whitequark.org ---
OK, having read that I suggest we follow the standard procedure. The new pysim
design should already handle this kind of logic loop just fine. I suggest you
make a (coarse) SRNAND latch out of normal (coarse) NAND cells, test that it
works correctly in your designs, and if it does not, file an MCVE over at the
nmigen repository. Then I investigate and fix any issues. The same with cxxsim
once it's ready.

Regarding hierarchical design slowdown: this is inevitable in the current pysim
architecture, but cxxsim can trivially use the Yosys flattening functionality
and does not suffer from any hierarchy-related issues.

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