[libre-riscv-dev] [Bug 274] New: Investigate how BSV performs Formal Verification and what can be Applied to FPUs

[bugzilla-daemon at libre-riscv.org]

http://bugs.libre-riscv.org/show_bug.cgi?id=274

            Bug ID: 274
           Summary: Investigate how BSV performs Formal Verification and
                    what can be Applied to FPUs
           Product: Libre-SOC's first SoC
           Version: unspecified
          Hardware: PC
                OS: Linux
            Status: CONFIRMED
          Severity: minor
          Priority: ---
         Component: Formal Verification
          Assignee: lkcl at lkcl.net
          Reporter: yimmanuel3 at gatech.edu
                CC: libre-riscv-dev at lists.libre-riscv.org
   NLnet milestone: ---

I believe BSV can generate formally verified adders.
I will soon take a look at how it handles formal verification.
This is mainly a research/investigation bug.

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