[libre-riscv-dev] [Bug 269] auto-conversion / parser of POWER ISA Spec v3.0B

[bugzilla-daemon at libre-riscv.org]

http://bugs.libre-riscv.org/show_bug.cgi?id=269

--- Comment #5 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
the way it works is:

* lexers (PowerLexer) and filters sort out python-style indentation
* parser (PowerParser) turns pseudo-code into an AST
* as part of that parsing, registers that were read and written to
  are noted
* all reg index numbers (fields - RA, RB) that were "read" from GPR
  are "yield" obtained from the opcode.
* a variable named after the field is dropped into the dictionary
  of code to be executed
* code is executed
* all reg index numbers that were "written" in the code are "yield"
  obtained (again), and, from the dictionary of exec()'d code,
  the value is obtained, then stored in the "regfile".

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