[libre-riscv-dev] power pc

[Jacob Lifshay]

On Thu, Oct 31, 2019, 14:34 Luke Kenneth Casson Leighton <lkcl at lkcl.net>
wrote:

> On Friday, November 1, 2019, Jacob Lifshay <programmerjake at gmail.com>
> wrote:
>
> > On Thu, Oct 31, 2019, 14:08 Luke Kenneth Casson Leighton <lkcl at lkcl.net>
> > wrote:
> >
> > > On Thu, Oct 31, 2019 at 8:57 PM Jacob Lifshay <
> programmerjake at gmail.com>
> > > wrote:
> > >
> > > > from reading the Power spec and Linux source, Power saves and
> restores
> > > all
> > > > registers in a similar fashion for interrupts (there aren't any
> > mips-like
> > > > reserved-for-os GPRs).
> > >
> > > gooood.  oh - could you send me a link to some git-browse-tree-thing
> > > which references the power context-switch source (and line)?  i'll put
> > > it in the wiki.
> > >
> > the exception entry point:
> > https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/
> > linux.git/tree/arch/powerpc/kernel/exceptions-64s.S?h=v5.4-rc5#n409
> >
> > the rest of the context switch code is in a different file:
> > https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/
> > linux.git/tree/arch/powerpc/kernel/entry_64.S?h=v5.4-rc5#n589
>
>
> Okaay that's interesting.
>
> Is r0 a standard register (ie not hardcoded to 0x00000) on PowerISA?


yes.

If so
> it can be used to do "stuff" without damaging x1-x31 from RV.
>
> Also looks like r1 is SP on PowerISA where x2 is SP on RV.
>

yes. also, power has a separate link register where RV just uses x1.

maybe rv x1 should be mapped to the link register (assuming it doesn't have
any reserved bits or encodings) then power regs 0 and 1 can be mapped to
the most commonly used RV csrs (fp status reg? probably won't work due to
being read/modified by every fp instruction) or used as scratch registers
for the power exception handlers.

Jacob