[libre-riscv-dev] power pc

[Jacob Lifshay]

On Thu, Oct 31, 2019, 11:36 Luke Kenneth Casson Leighton <lkcl at lkcl.net>
wrote:

> On Thu, Oct 31, 2019 at 7:58 AM Jacob Lifshay <programmerjake at gmail.com>
> wrote:
> >
> > On Thu, Oct 31, 2019, 00:39 Luke Kenneth Casson Leighton <lkcl at lkcl.net>
> > wrote:
> >
> > > Hiya Jacob
> > >
> > > Realised that the tricky bit will be the context switch: CSRs,
> registers.
> > > Can you put some thought into how to do that?
> > >
> >
> > sure. my initial plans are that the power and riscv integer and fp
> > registers are the same (I think they both have 32 64-bit registers for
> each
> > of int/fp).
>
> yehyeh. we could hypothetically map them to the higher-numbered
> registers (32-63, 64-95, 96-127) which will keep them out of the way
> of the POWER ones.
>

well, I had intentionally wanted to map risc-v x1 to x31 to power's integer
register 1 to 31 and risc-v f0 to f31 to power's fp reg 0 to 31. that
allows using standard power instructions to save and restore state to also
save and restore the risc-v registers rather than needing the risc-v
extensions to depend on SV extending the register numbers. that also
simplifies the code needed to handle syscalls and (if they're are
implemented) inter-architecture function calls.

>
> >All the other riscv registers (all csrs?) will map to power's
> > equivalent of csrs or, if all else fails, will be memory-mapped as
> per-cpu
> > memory (same address on every cpu, accessing it goes to local cpu). will
> > have to check.
>
> CSRs would be better otherwise it interferes with the memory-address
> logic (special-case).
>

yeah

Jacob