[libre-riscv-dev] power pc

Jacob Lifshay programmerjake at gmail.com
Thu Oct 31 07:57:48 GMT 2019

On Thu, Oct 31, 2019, 00:39 Luke Kenneth Casson Leighton <lkcl at lkcl.net>

> Hiya Jacob
> Realised that the tricky bit will be the context switch: CSRs, registers.
> Can you put some thought into how to do that?

sure. my initial plans are that the power and riscv integer and fp
registers are the same (I think they both have 32 64-bit registers for each
of int/fp). All the other riscv registers (all csrs?) will map to power's
equivalent of csrs or, if all else fails, will be memory-mapped as per-cpu
memory (same address on every cpu, accessing it goes to local cpu). will
have to check.

> Bear in mind though that, for now, we're entirely off-book as far as NLnet
> funding is concerned ok?


Jacob Lifshay

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