[libre-riscv-dev] power pc

Jacob Lifshay programmerjake at gmail.com
Tue Oct 29 21:54:58 GMT 2019

On Tue, Oct 29, 2019, 14:08 Luke Kenneth Casson Leighton <lkcl at lkcl.net>

> On Tue, Oct 29, 2019 at 8:16 PM Michael Pham <pham.michael.98 at gmail.com>
> wrote:
> > Does this mean that all these use cases will suffer from less
> > efficiency if you do decide to switch to POWER?
> that's what i really want to know.

Efficiency would depend on usecases (like usual). I'm making an educated
guess that the code would run slower in some important cases, and I know
for sure that there is a code-size penalty (which implies a power penalty
due to larger number of instructions that need to be read from the i-cache
and decoded and scheduled). there's probably not a need for larger i-caches
due to code-size because there aren't generally a lot of atomic
instructions, some of them just happen to be in hot loops.

> > That seems like a huge downside honestly given how important C++11 is.
> > Maybe just stick with RISC-V instead?
> ohhh hell no.  if Hugh gets back to me that the other OpenPower
> Members (NXP, IBM etc.) are ok with the "breakout" system
> (ISANS/ISAMUX), in an "official" capacity, it's worth it, just for the
> acceptance.

I think that if we decide we should go with a PowerISA implementation, that
we should at least support user-mode RV64GC code for compatibility, because
we have risc-v in our name, and because of being simple to implement.

If all the above happens I'm fine with proceeding to switch to Power -- I'm
not strongly for or against it.

> we can then always design and add c++-atomic-compatible instructions
> (if it turns out that the implementation of standard power-atomics is
> really that awkward).

sounds good, though we should try to standardize them, since we wouldn't be
the only ones who would benefit from better atomics.


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