[libre-riscv-dev] power pc
Luke Kenneth Casson Leighton
lkcl at lkcl.net
Wed Oct 23 15:31:31 BST 2019
On Wednesday, October 23, 2019, Jacob Lifshay <programmerjake at gmail.com>
> one other unusual thing about Power, the FP status register has a
> whole pile of additional fp status bits that are set by operations,
> implementations will need to calculate all the extra bits (not hard,
> just means we can't use the FP units we developed without
FPCSRs all have to be added anyway.
> Also, 32-bit floats are stored in the FP registers in 64-bit format
> (but otherwise behave like 32-bit floats should), this means it will
> be more complex to store multiple smaller FP values in a single FP
I thought about that, and one solution is that, just as with SV on RV, if
vectorisation is enabled the data is packed in and any top bits of
registers not touched.
ie exactly as is already done, therefore there is no conversion performed,
therefore there is no problem.
What is a problem however is that FCVT does not exist (because the
conversion is always implicit).
Therefore we would need to add FCVT.H.F FCVT.H.D FCVT.D.F FCVT.D.H and so
on which would be null operations when regs are marked as scalar-scalar but
would have actual real meaning when regs are marked as vector.
Another thing that needs to be properly thought through.
crowd-funded eco-conscious hardware: https://www.crowdsupply.com/eoma68
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