[libre-riscv-dev] [Bug 139] Swizzle needs to be high priority capability in ISA

[bugzilla-daemon at libre-riscv.org]

http://bugs.libre-riscv.org/show_bug.cgi?id=139

--- Comment #72 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
I cannot think why it took me 18 months to come up with the following idea:

Instead of having separate entries per register in the VBLOCK CAM formats,
where each register is 5 precious bits wasted, have 1 reg, 2 reg, 3 reg and 4
reg variants that permit the detection to be triggered by *one* reg (eg rd) and
apply to *multiple* regs, rd, rs1, rs2, rs3.

This should save a huge amount of space.

In the case of swizzle it means being able to put the entire swizzle group into
under 24 bits, 29 including the reg it is to be "activated" on.

Lots to think about on the flight.

-- 
You are receiving this mail because:
You are on the CC list for the bug.