[libre-riscv-dev] [Bug 139] Add LD.X and ST.X? Strided

[bugzilla-daemon at libre-riscv.org]

http://bugs.libre-riscv.org/show_bug.cgi?id=139

--- Comment #70 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
(In reply to Jacob Lifshay from comment #69)

> > No wonder GPU ISAs are enormous.
> 
> They generally don't care about code size...

1k executables, handling 4x or 8x data workloads, I am not surprised.


> > That deals with the ALUs, although it leaves SVP with a "hole" (no
> > equivalent in SVP to VBLOCK swizzle capability, at the moment).
> 
> I would be surprised if we couldn't cram a simplified swizzle field (8 bits
> for swizzle, 1-2 bits to allow specifying which src reg is swizzled) into
> SVP64, if not we can always define a SVP80 format, though at that point it
> may be better to just use macro-op fusion. :)

:) and I use the ennntiire 80+ opcode space for VBLOCK. yes, i knoooow... 

Would you like to take a look at redesigning SVP64 to add 1 bit so that it can
flip between swizzle mode and VLEN mode? the simplest option is to lose the
extension of reg nums to 7 bits, that frees up as much as 4 bits

Or, if only some bits (not all) are discarded (particularly in FR4) then one
clear bit can be freed up in the column marked "reserved" and that can be
turned into a swizzle-or-VL selector.

Again to cram in as much as possible I am kiinda liking the "4 x 2bit swizzle
plus 1 bit to say if it is consts or xyzw" thing. It would also allow space for
a destmask.

No room for 2x swizzles sadly, unless a mode for specifying regs is also added.
Can I leave that with you to think through?

Oh i wrote the swizzle consts up in VBLOCK, arbitrarily picked some consts, to
see what it looks like, do let me know what you think.

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