[libre-riscv-dev] [Bug 139] Add LD.X and ST.X? Strided

[bugzilla-daemon at libre-riscv.org]

http://bugs.libre-riscv.org/show_bug.cgi?id=139

--- Comment #56 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
ahhh i GOT it:

https://gitlab.freedesktop.org/panfrost/mali-isa-docs/blob/master/Midgard.md

Load/store words

13-16: mask
17-24: swizzle

ALU ops:

15-22: input 1 swizzle
if "input 2 inline constant" set:
    28-35: inline const 0-7
else:
    28-35: input 2 swizzle
40-47: write mask
    2 bits for each output when 32-bit, 1 bit when 16-bit

so they have 2 possible swizzles for inputs, and, crucially, the write
mask will be what says which of the input bits get ignored.


therefore as long as we can add a dest-mask, SUBVL *is* the DESTSUBVL.
DESTSUBVL *is* SUBVL.

a src mask is indeed unnecessary.


SUBVL-predication mode idea
----------------------

one possible solution here is to (somehow) jam in a mode which says
"hey, you know we said SUBVL doesn't have predication, and that the
predicate bit applies to *all* of SUBVL? well, um, for this operation,
it does".

what that would do is limit VL to a maximum of around 16, but i'm fine
with that.


8-bit-swizzle idea
-------------

going back to 8-bit on swizzle rather than 12-bit, the remaining 4 bits
can be used as a predicate SUBVL immediate DESTMASK.

that solves the issue of whether it's run-time safe (in the immediate
case).

also, with DESTSUBVL being redundant (directly equivalent *to* DESTMASK)
that gives two bits back [useable for other opcodes]

i'd really like to know why other GPUs only have 8-bit swizzle,
rather than having constants.  is setting from constants that common
that they really *need* special treatment?


SVP for 1 swizzle, opcode for the other idea
---------------------------------------

we definitely do not have room to fit 2 swizzles (16 bit) and it seems
from Midgard that they're certainly needed.

VBLOCK covers the multi swizzle scenario fine, but SVP does not.
if one swizzle immediate can be jammed into the SVP64 prefix,
the other can be in the operation.  if the SVP64 swizzle prefix is not
used, the "rules" state that the same swizzle (in the opcode)
applies to *both* operands.

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