[libre-riscv-dev] [Bug 139] Add LD.X and ST.X? Strided

[bugzilla-daemon at libre-riscv.org]

http://bugs.libre-riscv.org/show_bug.cgi?id=139

--- Comment #44 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
(In reply to Jacob Lifshay from comment #43)
.
> > 
> > predication can be pseudo-added by:
> > 
> > if (sel_field == 0b111) continue.
> 
> if we're going to do that, we really should increase the field size to 4
> bits per element, since shuffle2 already uses them all (rs1 x, y, z, and w
> and rs3 x, y, z, and w)

Yes was just thinking that. Then shuffle could keep 3 bits for consts and xyzw
and use the 4th bit for predication

> 
> though I am extremely disinclined to have something that sets the output
> subvl in a data-dependent way (basically the output type & complete layout),
> that seems like a giant mess of security vulnerabilities just waiting to
> happen.

Already sorted the algorithm was designed and implemented successfully in
spike, for twin predication, last year (albeit for VL not SUBVL)

It is shown in the appendix pseudocode as well. The src idx and dest idx are
incremented independently and BOTH will result in loop termination on reaching
SUBVL.

> also, what do you do when subvector 1 has 2 ignores, subvector 2 has 3
> ignores, subvector 3 has 1 ignore, and so on?!

Stop the loop when either of the subindices reach SUBVL.

If the programmer fails to insert enough ignores to not "represent" differing
SUBVLs, that is their lookout. They should have read the manual :)

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