[libre-riscv-dev] [Bug 139] Add LD.X and ST.X? Strided

[bugzilla-daemon at libre-riscv.org]

http://bugs.libre-riscv.org/show_bug.cgi?id=139

--- Comment #39 from Jacob Lifshay <programmerjake at gmail.com> ---
(In reply to Jacob Lifshay from comment #38)
> (In reply to Jacob Lifshay from comment #36)
> > (In reply to Luke Kenneth Casson Leighton from comment #35)
> > > i'm not able to say because i really do not understand how swizzle2 works.
> > > i've spent several days researching it and simply cannot find anything,
> > > not even based on the hints of swizzle2 being in LLVM IR.
> > > 
> > > can you please describe it in pseudocode in a simple loop?
> > 
> > sure.
> > 
> > https://play.rust-lang.org/?version=stable&mode=debug&edition=2018&gist=fa181fd305c70bde0372e0d99d873685
> > 
> > swizzle2 rd, rs1, rs2, rs3
> 
> There's also the swizzle instruction:
> 
> https://play.rust-lang.org/
> ?version=stable&mode=debug&edition=2018&gist=17d9891a5ceae49402a948f2cbf29ba6
> 
> swizzle rd, rs1, rs2

well, won't bother to fix the bugs in both instructions' example code :)
(inverted condition, if in wrong place, probably more)

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