[libre-riscv-dev] [Bug 139] Add LD.X and ST.X? Strided

[bugzilla-daemon at libre-riscv.org]

http://bugs.libre-riscv.org/show_bug.cgi?id=139

--- Comment #30 from Jacob Lifshay <programmerjake at gmail.com> ---
(In reply to Luke Kenneth Casson Leighton from comment #28)
> Remember also we are quite lucky in SV in that vec4 can be constructed from
> scalar registers. So we can cheat slightly in certain cases by mapping one
> FP32 vec2 to x8 and another to x9, then treat x8 as a vec4.

that only works when VL=1, since the elements are packed tightly.

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