[libre-riscv-dev] [Bug 139] Add LD.X and ST.X? Strided

[bugzilla-daemon at libre-riscv.org]

http://bugs.libre-riscv.org/show_bug.cgi?id=139

--- Comment #27 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
rs2 subvl=1 makes sense, i was just looking at CORDIC and SLERP and they need
the same trick.

An extra SUBVL just is not that simple.

It would be better to have swizzle2, swizzle3 and swizzle4 to truncate the
subvector.

Noted about identity.

The alternative is to have a "ignore" swizzle enum value.

Ignore, identity, 0, 1, x y z w

Ignore basically brings back bit level predication on the SUBVL elements.

It then becomes possible to combine ignore at either the start or the end in
order to copy data from vec4 to vec2 or vec2 to vec4, by treating *both* as a
vec4 and "ignoring" 2 of the subelements.

Adding special SUBVL CSRs just for this one case is really not a good idea.
Every extra CSR risks increasing beyond the 32/64 bits, resulting in greater
context switch latency.

If however more than one op turns out to need it and there is no "workaround"
we can reevaluate that.

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