[libre-riscv-dev] [Bug 139] Add LD.X and ST.X? Strided

[bugzilla-daemon at libre-riscv.org]

http://bugs.libre-riscv.org/show_bug.cgi?id=139

--- Comment #19 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
i just managed to visualise the example that i saw.  it was of two
vectors where the "swizzler" (selector) was twice the length of
each of the individual vectors.

the example contained two vec4 args plus a swizzle array of *eight*
selectors, where the first four were applied to src1 and the last
four were applied to src3.

that means we need to use arguments for the selector (src2) of up
to 24 bits.

it also means that the destination vector is *twice* the length of the
src registers, which is not something that's been taken into consideration.

this is sufficiently weird that i'm concerned about the complexity
in hardware: it would be literally *the* only hardware-level instruction
where rules on VL length had to be violated (made non-uniform)

panfrost only has 8-bit swizzle specifiers:
https://gitlab.freedesktop.org/panfrost/mali-isa-docs/blob/master/Midgard.md

i'm wondering if this is just too complicated and what assembler would
look like, with and without the full swizzle/swizzle2 (3*SUBVL) capabilities.

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