[libre-riscv-dev] PowerISA and maybe vhdl to nmigen converter

[Luke Kenneth Casson Leighton]

On Tuesday, November 26, 2019, Tobias Platen <hacks2019 at platen-software.de>
wrote:

> I'm interested in comparing the PowerISA with RISCV. Therefore I first
> will have a look at microwatt[1], a tiny Open POWER ISA softcore written in
> VHDL 2008.


yes this was written by anton blanchard, a former colleague and friend of
hugh blemings, Director of OpenPOWER foundation

Previously I have only used Verilog so VHDL is now to me.


i find it so obtuse, it is nuts. functions appear to be incomplete, all the
time.  verilog is at least readable.
sigh.


> I might write a VHDL to nMigen converter if it is useful.


maaybe.  actually you might be able to use yosys to convert from VHDL to
ilang then ilang to verilog. from there sv2nmigen can take over.

so hypothetically it should not be needed.

l.



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