[libre-riscv-dev] [Bug 146] create python bindings to reference FP implementation
bugzilla-daemon at libre-riscv.org
bugzilla-daemon at libre-riscv.org
Tue Nov 19 16:11:37 GMT 2019
http://bugs.libre-riscv.org/show_bug.cgi?id=146
--- Comment #7 from Jacob Lifshay <programmerjake at gmail.com> ---
getting started switching to simple_soft_float:
installation instructions:
install rust using rustup (you probably already did that).
create cpython 3.5 to 3.7 virtualenv (not sure if 3.8 is supported yet)
install python bindings build tool:
pip install maturin
get source:
git clone https://salsa.debian.org/Kazan-team/simple-soft-float.git
cd simple-soft-float
change source dir to use specific version of rust nightly:
(must be in simple-soft-float dir):
rustup override set nightly-2019-07-19
build & test (like setup.py develop):
cargo test --features python # runs tests from Rust
# build and install to python
maturin develop --cargo-extra-args="--features python-extension"
python -m unittest # runs smoke tests from Python
build Rust docs:
cargo doc --features python # ignore warning about rand_core name collision
open docs in default browser:
xdg-open target/doc/simple_soft_float/struct.DynamicFloat.html
build python docs:
pip install pdoc3
pdoc3 simple_soft_float --html -o target/python-docs
xdg-open target/python-docs/simple_soft_float.html
Example code for FP add:
import simple_soft_float as ssf
# note 2 underlines in PlatformProperties_RISC_V,
# caused by PyO3 issues with not supporting constant static
# members of classes. Will eventually switch to
# PlatformProperties.RISC_V when fixed.
platform = ssf.PlatformProperties_RISC_V
f32_properties = ssf.FloatProperties.standard(32, platform)
a_bits = 0x7F800000 # bits of 1.0f32
b_bits = 0x7F800000
# construct 32-bit floats from bits
a = ssf.DynamicFloat(properties=f32_properties, bits=a_bits)
b = ssf.DynamicFloat(properties=f32_properties, bits=b_bits)
result = a + b # compute sum
result_bits = result.bits # get bits of result
assert isinstance(result_bits, int)
All the other settings can be ignored for now since our HW doesn't implement
handling status flags yet.
--
You are receiving this mail because:
You are on the CC list for the bug.
More information about the libre-riscv-dev
mailing list