[libre-riscv-dev] power pc

Jacob Lifshay programmerjake at gmail.com
Fri Nov 1 02:15:29 GMT 2019

On Thu, Oct 31, 2019, 11:36 Luke Kenneth Casson Leighton <lkcl at lkcl.net>

> On Thu, Oct 31, 2019 at 7:58 AM Jacob Lifshay <programmerjake at gmail.com>
> wrote:
> >All the other riscv registers (all csrs?) will map to power's
> > equivalent of csrs or, if all else fails, will be memory-mapped as
> per-cpu
> > memory (same address on every cpu, accessing it goes to local cpu). will
> > have to check.
> CSRs would be better otherwise it interferes with the memory-address
> logic (special-case).

Turns out that power supports SPRs (the equivalent of CSRs), it uses a
10-bit identifier for which SPR to access so there's not as much space.
There should definitely be enough space to fit the user-visible RV64GC CSRs.

There's a table of them in the PowerISA spec v3.0B in Figure 18 starting on
page 971 (page 989 in the pdf).

don't you just love documents that don't start on page 1 :)



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