[libre-riscv-dev] multi issue

[Luke Kenneth Casson Leighton]

to put it into perspective, jacob, think through the timescales:

current (ish) plan, 48-bit SV, 32-bit SV-RVC, 32-bit RVGC:

* appx 3 weeks to finish SV spec
* appx... 2-3 weeks to implement instruction decode engine (based on
existing code)
* appx 3-4 weeks to implement SV hardware-loop.

maybe another month on that for debugging and wiggle-room, above
assumes that the actual instruction "actioning" engine is all
completed.

compare to this:

* 1 to 6 months discussion on the new variable-length format (most of
it waiting for other people to respond)
* hand-over to RISC-V Foundation for ratification AT WHICH POINT WE
ARE COMPLETELY EXCLUDED FROM ALL DISCUSSIONS.
* ratification to take maybe another YEAR (during which time we have
NO IDEA if the specification has been changed AND THE MEMBERS ARE
PROHIBITED FROM DISCUSSING THAT WITH US)

... you see how that works?

so we can either go ahead now, or we can delay the project by
approximately 2 years, by which time NLNet's EU funding will have run
out.

l.