[libre-riscv-dev] multi issue

[Jacob Lifshay]

On Thu, May 30, 2019, 16:04 Luke Kenneth Casson Leighton <lkcl at lkcl.net>
wrote:

> On Thu, May 30, 2019 at 11:58 PM Jacob Lifshay <programmerjake at gmail.com>
> wrote:
>
> > we will additionally need to decide which variety of long instruction
> > encoding we will support: the encoding in the original spec or the new
> > encoding proposed by clifford wolf.
>
>  both, by using the mvendorid-marchid-isamux scheme that i created
> last year.  the isamux scheme is identical to that used by PowerPC to
> dynamically swap from big-endian to little-endian, generalised.
>
>  that's if there are any instructions in the extended format that we
> actually need.
>
Our custom 48 and 64-bit instructions will need to fit in the encoding
scheme.

>
> > The way I had been planning on decoding multiple instructions is to read
> > multiple 16-bit units from the instruction cache, then, for every unit,
> > calculate the length of the instruction that might start at that unit,
> then
> > calculate which units actually start instructions for the first N
> > instructions, where N is the max decode count, then mux the instructions
> > into N ILEN-bits slots where each slot additionally has a valid bit. the
> N
> > slots then can be then enqueued into the instruction queue.
>
that was intended to be the pre-vectorization queue.

>
>  multiplied by the element vectorisation length.
>
> > the fetch
> > address would then be updated by the number of units that were
> successfully
> > added to the queue.
>
>  without the element vectorisation length as a multiplier.
>
>  it's really quite involved.
>
> l.
>
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