[libre-riscv-dev] Interesting video about voltage regulator design for CPUs

[Luke Kenneth Casson Leighton]

On Thu, May 30, 2019 at 4:43 AM Jacob Lifshay <programmerjake at gmail.com> wrote:
>
> https://youtu.be/Y4-78_a33Fo

 from the years dealing with PCB layout using embedded processors, the
usual way is to have a PMIC that the processor communicates with
through I2C.  the PMIC in particular handles the NMI# signal, a good
example which is extremely low-cost is the AXP209.

 through I2C requests, the PMIC can easily be requested to crank up
the voltage for different domains (the main core voltage being the
critical / relevant one), and, once that's done, the processor can
increase the clock speed.

 does the video basically say that if the voltage isn't high enough,
the transistion of gates at faster clocks takes so long and/or draws
so much power that you risk draining both the external capacitors and
the internal capacitance, with a resultant drop in voltage that goes
below the trigger threshold for the transistors?

 increasing the voltage compensates for that, and, at lower clock
rates is just a "waste of power".  so you don't have to worry about
the slow speed of the I2C interface to the PMIC, basically.

 having the voltage setting taken care of by an *external* PMIC is a
cheaper (well-known) solution, btw.  documented examples here:

https://libre-riscv.org/shakti/m_class/peripheralschematics/

l.