[libre-riscv-dev] [Alliance-users] Coriolis flow fails on Arlet verilog MOS6502 core

[Jean-Paul Chaput]

On Sat, 2019-05-25 at 14:22 -0700, Samuel Falvo II wrote:
> I'm not sure this will be of any help or use, but the original KCP53000
> processor uses an instruction decoder which is almost built using the same
> PLA-style decoder that the 6502 uses (absolutely no pipelining at all).  I've
> had no problems with ArachnePNR successfully elaborating a design for the
> iCE40HX8K FPGA.  

  FPGA vs. ASIC is an interesting debate.

  They face very similar algorithmic problems of P&R and partitioning but
  with different end results. One difference is that the "density" of logic
  inside a FPGA (the LUTs) is known beforehand. So one of the first task
  of a synthesiser is to partition the netlist so it fit it then perform
  a placement on the LUTs so the routing capacity is not exceeded.

  On the other hand, the placer of Coriolis is not "density aware". It crams
  the cells together to minimize the total wire length (without cell overlap).
  This is good, but sometimes laeds to very high density area. And the
  Coriolis global+detailed router is not got enough (yet) to manage all
  of them. I'm working on that...

  So it is not surprising that it works on FPGA, not straight away with
  Coriolis (works with tuning). One interesting question would be how
  saturated are the FPGA LUT with this synthesis. It would give an idea
  of the efficiency/difficulty of the synthesis.

  Best regards,
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