[libre-riscv-dev] [hw-dev] Re: 6600-style out-of-order scoreboard designs (ariane)

[Luke Kenneth Casson Leighton]

it's working!  the dependency-matrix version (FU-Regs + FU-FU) is
actually working.  for a given definition of "work".

at the moment, there is a bug where if an instruction uses a src
register also as a dest register, the matrices believe that this is
both a read-hazard (on itself) *and* a write-hazard (on itself).  this
because the test for read-dependencies and the test for
write-dependencies is in the same clock cycle.

whoops.

this is very hard to distinguish from the case where there are e.g.
three instructions:

ADD r1 r2 r3
ADD r3 r3 r3
ADD r3 r4 r5

* instruction 2 depends on instruction 1 (RaW)
* instruction 3 depends on instruction 2 (WaR)

if however the testing of read dependencies was done on a *separate*
clock cycle (one earlier) from write dependencies, there may be an
opportunity to detect that the middle instruction is not dependent on
itself.

i have a suspicion that the CDC6600's use of major-minor clock cycles
on read-register and write-register *may* also be responsible for
ensuring that.

this is going to take some time to investigate.

l.