[libre-riscv-dev] [Bug 44] IEEE754 FPU inverse-sqrt
    bugzilla-daemon at libre-riscv.org 
    bugzilla-daemon at libre-riscv.org
       
    Sat May 18 20:09:39 BST 2019
    
    
  
http://bugs.libre-riscv.org/show_bug.cgi?id=44
--- Comment #23 from Jacob Lifshay <programmerjake at gmail.com> ---
(In reply to Luke Kenneth Casson Leighton from comment #22)
> CSA 3-2:
> -------
> 
> SUM = A XOR B XOR C
> CRY = NAND(NAND (A,B), NAND(B,C), NAND(A,C))
> 
> CSA 4-2:
> -------
> 
> S0, Cout = CSA32(A,B,C)
> SUM, CRY = CSA32(S0, D, Cin)
> 
> that err seems to be it, where normally there would be 5 inputs
> and 3 outputs (Cin ripples through to Cout).
> 
> so err it's not CSA 4-2 at all, it's CSA 5-3 (oink?)
> 
> CSA 4-2 would presumably be much simpler?
it's csa 4-2. notice that there isn't a path from cin to cout.
I personally prefer csa 3-2 since it takes half as much logic but adds more
than half as many inputs for the same number of outputs, so it's more
efficient.
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