[libre-riscv-dev] [Bug 44] IEEE754 FPU inverse-sqrt

bugzilla-daemon at libre-riscv.org bugzilla-daemon at libre-riscv.org
Sat May 18 11:00:54 BST 2019


--- Comment #21 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
i found an expired patent

which at the very least contains links to prior art that
describe a 4-2 CSA and a 3-2 CSA adder.

if that's correct, it just leaves the "DS" function - "Digit Select"
which is described as "a 6-bit carry-propagate adder and simple
constant value comparators".

so the input would appear to be in a redundant (carry-save) form,
that has to be added up in order to make the comparison to see
if it's within 2 specified ranges.

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