[libre-riscv-dev] [Bug 60] N-stage 64-bit multiplier pipeline needed (signed/unsigned)

[bugzilla-daemon at libre-riscv.org]

http://bugs.libre-riscv.org/show_bug.cgi?id=60

--- Comment #7 from Jacob Lifshay <programmerjake at gmail.com> ---
I implemented the multiplier, it passes all tests.
I don't have any tests for having pipeline registers in the multiplier yet.
I also didn't yet add the adder input for FMA, that should be relatively
trivial.
I also need to add additional documentation.

The multiplier supports every combination of aligned 8/16/32/64 that fits in
64-bits. For each part, it supports all 4 RISC-V multiply ops: mul, mulh,
mulhsu, and mulhu.

Review and comments welcome.

The code is at
https://salsa.debian.org/Kazan-team/simple-barrel-processor/blob/master/src/multiply.py
The tests are at
https://salsa.debian.org/Kazan-team/simple-barrel-processor/blob/master/test/test_multiply.py

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