[libre-riscv-dev] [hw-dev] Re: 6600-style out-of-order scoreboard designs (ariane)

Luke Kenneth Casson Leighton lkcl at lkcl.net
Fri May 17 06:41:05 BST 2019


On Thu, May 16, 2019 at 5:42 PM Mitchalsup <mitchalsup at aol.com> wrote:
>
> Luke,
>
> You did stumble over a bug. Consider the following instruction::
>
>      ADD     R7,R7,R3
>
> When this is issued into the FU, there are Read_Pending on R3 and R7 and
> a Write_Pending on R7. But the Write to R7 is necessarily subsequent to the
> read of R7. {And that is why your added gate sort-of-works}
>
> What we really want is for that instruction to wait for any OTHER writes
> to R7 and then it can assert its Write Reservation on R7 but it should never
> be dependent on itself.

 i think this is what the FU-FU dependency matrix is for: to capture
the inter-FU write and inter-FU read dependencies on the *correct
clock cycle*.

 the global read-pend and write-pend vectors are too general, and
don't capture the crucial information that results in cyclic
dependencies.

 the FU-FU dependency matrix effectively has a *per FU* variant of the
[global] read-pend and write-pend vectors which, due to them having
their own latches, take a snapshot of the read/write-pending state *at
that specific time*, for *that specific FU*.

 yes i took on board that the global read-pend and write-pend vectors
need to be one a one-cycle delay: this concept needs i think to be
applied to every FU, i.e. for every FU to have its own separate
read-pend / write-pend vector (just with the same one-clock delay)


> And you are reading figure 79 correctly--this is the depMatrix.

 okaaay.  so what *might* work is to go back to the original version
of the Function Unit (before i started messing about with it), and
drop in the FU-FU Dependency Matrix.

 going back to a quick flip between the images on pages 30 and 32
(10.6, 10.7) i believe the Function Unit is directly equivalent to the
FU-Regs Dependency Matrix: just in a slightly different form: the
decoding of the 3 registers (src1/src2/dest) from binary into unary is
the equivalent of the Dependency Cell 3 latches, and the AND followed
by the big OR gates is the equivalent of that diagram 79 from
Thornton, which is one row of the FU-Regs Dependency Matrix generating
the read/write pending vector (11.4.7 top of p29).

i hope. :)

i'll see how it goes.

thx mitch.

l.
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